1. Field of the Invention
The present invention relates to the field of producing semiconductor devices and particularly to the field of generating several semiconductor devices in parallel.
2. Description of the Prior Art
Generating semiconductor devices in parallel on a substrate is well-known in semiconductor technology. Thus, for example in a BICMOS process, a specific sequence of processor steps is passed to generate CMOS and bipolar transistors on a semiconductor substrate. A possible BICMOS process is described, for example, in Widmann, Mader, Friedrich, “Technologie hochintegrierter Schaltungen”, Springer Verlag, 2nd edition, 1996.
While BICMOS processors allow relatively many steps in a parallel processing for the production of CMOS and bipolar transistors with low integration density, for the production process for CMOS and bipolar transistors with high integration densities, currently, methods are used where the process steps for CMOS and bipolar transistors are mainly sequenced successively. For example, during the production of certain parts of the bipolar transistor, the CMOS transistors are covered with one or several layers to limit the effect of the specific process steps merely to the area of the CMOS transistors.
By successivly sequencing bipolar and CMOS process blocks, during the manufacturing process, a stripe with a width of several micrometers of deposited layers builds up between bipolar and CMOS transistors, which prevents a denser packing of bipolar and CMOS transistors.
Further, the CMOS and/or bipolar transistors are subject to a higher thermal stress than in a pure CMOS or bipolar process, since they are additionally subject to the process temperatures of the production steps for generating the other device. Due to the tendency in newly developed bipolar or CMOS transistors towards larger and larger dopant gradients, i.e. to constantly flatter dopant profiles, these transistors react sensitively to the additional thermal stress. Further, a mechanical tension is imparted on the devices covered with one or several layers by the thermal stress, which can lead particularly in the newly developed transistors with a flat profile to a deterioration of the devices in comparison to a production with a pure bipolar or CMOS process.
It is thus desirable to provide a method for a parallel production of devices of different types, which enables producing the devices with a high integration density and where method steps are performed with a high parallelism.
Further, it is desirable to reduce thermal stress and mechanical tension in a parallel production of semiconductor devices of different types.